Understanding RDRAM

RDRAM is basically known as Rambus RAM,it is really more of a bus interface architecture than DRAM architecture.Rambus buses uses multiplexed address/data lines to connect the memory controller to the RDRAM device.The specification of this interface states that clock must runs at 300 mHz.In addition to this,th dat is latched on both rising and falling edge of the clock.Using such a bus,theoretically, transfer rate of 600 million cycles is possible.In addition each 64-Mbit RDRAM is broken into four banks each with its own row decoders.So,at any given time,four pages remain open.The RDRAM protocol is packet driven,where address packets are followed by data packets.